1. Field of the Invention
The present invention relates in general to a defect detection system and method, and more particularly, to a defect detection system and method capable of outputting a multilevel signal for identifying defects.
2. Description of the Prior Art
During the fabrication process, a wafer receives a number of doping, layering, patterning, and metallization steps. Each of these steps must meet exacting physical requirements. However, all steps have some variation from perfect calibration, thereby resulting in some variation on the wafer surface, especially while bringing up a new semiconductor fabrication process. Accordingly, a variety of yield monitors are required to determine the health of the process and to find systematic problems.
Several known conduction line structures, such as poly-crystal lines, diffusion lines, metal lines, and N-type or P-type well lines are subject to being detected for determining whether there are undesirable defects existing. Furthermore, there are electrical-isolated routes, each of which may comprise two adjacent and electrical-isolated conduction lines, subjected to being detected for determining whether there are undesirable defects existing. Once detected, these defects are analyzed in a process called failure analysis. During failure analysis, valuable information regarding problems with fabrication materials, process recipes, ambient air, personnel, and machines can be discovered. Therefore, detection of defects on an integrated circuit is critical to high yields and process control.
Please refer to FIG. 1, which is a schematic diagram showing a prior art defect detection system 100 for identifying defects in an integrated circuit. The defect detection system 100 comprises a sense amplifier 110, a pull-down transistor 115 having a gate furnished with an enable signal Venable, selection transistors 121 and 122, and a selection circuit 190. The gates of the selection transistors 121 and 122 are both electrically connected to the selection circuit 190 for performing a selecting process so as to select a test route 150 as a selected test route for testing. A test input terminal 140 is coupled to the selection transistor 122 for inputting an input voltage Vin.
The sense amplifier 110 has a first terminal for receiving an analog sensing signal Sanalog, a second terminal for receiving a reference voltage Vref, and an output terminal for outputting an output signal Sout. In general, the first terminal of the sense amplifier 110 and the test input terminal 140 are connected to two pluralities of selection transistors having all the gates connected to the selection circuit 190 respectively for selecting a certain test route from a plurality of test routes to be tested as the selected test route for testing.
However, the output signal Sout outputted from the sense amplifier 110 is fundamentally a two-level signal similar to one-bit signal in a digital system, which can be utilized only for identifying whether or not the selected test route has defects. Accordingly, operational flexibility of the defect detection system 100 is quite limited. That is to say, the prior art defect detection system 100 cannot meet requirements when multilevel output signals are preferred under some test situations.